New smart memory controllers for data centre computing

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Microchip Technology Inc has expanded its serial-attached memory controller portfolio with the new SMC 2000 series of Compute Express Link (CXL) based Smart Memory Controllers that allow CPUs, GPUs and SoCs to utilise CXL interfaces to connect DDR4 or DDR5 memory. This solution provides more memory bandwidth per core, more memory capacity per core, and reduces the total cost of ownership in the data centre by allowing modern CPUs to optimise application workloads.

The low-latency SMC 2000 16x32G and SMC 2000 8x32G memory controllers are developed to CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards, and support PCIe 5.0 specification speeds. The 16x32G is the industry’s highest-capacity controller with 16 lanes operating at 32GT/s and supports two channels of DDR4-3200 or DDR5-4800, greatly decreasing the needed number of host CPU or SoC pins per memory channel.

Typical CXL attached memory modules include 512GB of memory or more, delivering an effective mechanism to increase the memory bandwidth obtainable to processing cores. This new paradigm shift provides data centre operators with the ability to deploy a wider range of ratios for memory to CPU cores depending on their actual application needs, resulting in improved memory utilisation and lower TCO.

“Microchip is excited to introduce our first CXL-based serial memory controller device to the market,” said Pete Hazen, corporate vice president of Microchip’s Data Center Solutions business unit. “We identified CXL as a disruptive technology early on and were integral to the standard’s definition. Microchip’s continued presence in the memory infrastructure market underscores our commitment to improving performance and efficiency for a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications.”

“The CXL Consortium was founded with a vision to deliver to the industry an open standard that would accelerate next-generation data centre performance,” said Siamak Tavallaei, president, CXL Consortium. “We’re pleased to see Microchip, a valuable contributor to the CXL Consortium, deliver a CXL solution enabling a new ecosystem for high-performance, heterogeneous computing.”

Microchip’s SMC 2000 CXL-based memory controllers employ an innovative design that delivers Reliability, Availability and Serviceability (RAS) features to transform solutions to the next level of efficiency and performance. Through CXL connectivity, the SMC 2000 external memory controller enables a CPU or SoC to utilise a broad set of media types with different cost, power and performance metrics without integrating a unique memory controller for each type. For example, using an SMC 2000 controller with DDR-4 memory, advanced CPUs that only directly support DDR5 can now also re-use DDR-4 memory expansion. The dual signature authentication and Trusted Platform support, secure debug, and secure firmware update ensure the SMC 2000 CXL-based controller family also meets all critical storage and enterprise application security needs.

Data centre application workloads require future memory products that can deliver the same high-performance bandwidth, low latency and reliability of today’s parallel-DDR-based memory products. The CXL platform is one of the biggest industry disruptions in recent years, bringing to market a new standard serial interface for CPUs to expand memory beyond the parallel DDR interface to provide the next level of efficiency and performance to the data centre.

Development Tools

To support our customers in building leading-edge systems that are compliant with the CXL standard, the SMC 2000 comes with design-in collateral and our ChipLink diagnostic tool that provides extensive debug, diagnostics, configuration and analysis tools with an intuitive GUI.

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